Research

Vectorize the impossible.

My PhD work explores how RISC-V vector architectures and FPGA platforms can make post-quantum cryptography faster, more efficient, and implementation-aware.

Classic McEliece, accelerated from algorithm to architecture.

Leiden University • 2021—Present

My research spans manual vectorization, finite-field arithmetic, optimized microarchitecture, and performance evaluation on Spike and AMD Alveo U250. The work bridges cryptographic correctness with the realities of data movement, parallelism, and timing.

Publications

A Survey of Recent Developments in Testability, Safety, and Security of RISC-V Processors

ETS ’23

Optimized AES with RISC-V Vector Extension

DDECS ’24

RISC-V based Vectorization of Classic McEliece Key Generation

SAMOS ’25

Speeding Up Bernstein’s Formulas for Permutation Networks through RISC-V based Vectorization

ARCS ’26

Classic McEliece Encapsulation and Decapsulation Acceleration using RISC-V Vectorization

Submitted ’26

Research building blocks

Parallelization strategies, vector instruction mapping, scheduling, and architecture-aware optimization for compute-intensive cryptographic workloads.

Optimized implementations of algebraic kernels that dominate code-based cryptography, including constant-time and side-channel-aware considerations.

AES, TDES, Reed-Solomon, convolutional encoding, and Viterbi decoding developed and verified across RTL and synthesis flows.