Selected portfolio • 2013—2026
Systems built end to end.
From research-grade acceleration to production FPGA platforms—architecture, RTL, verification, timing closure, integration, and bring-up.
Research • RISC-V V • 2026
Permutation Network Vectorization
Accelerating Bernstein’s formulas for 16×16 Benes networks through RISC-V vector extensions.
PQC • FPGA • Alveo U250
Classic McEliece Acceleration
Architecture-aware vectorization of key generation, encapsulation, and decapsulation.
FPGA • DSP • Platform engineering
Real-time Signal Processing Platforms
Low-latency DSP pipelines, multi-channel acquisition, PCIe, DDR, SERDES, and custom-board bring-up across Zynq and Kintex-7.
RTL • Security • Verification
Cryptographic RTL Systems
AES, TDES, Reed-Solomon, convolutional encoding, and Viterbi decoding developed through reusable RTL flows.