Principal FPGA Engineer • RISC-V Researcher

HardwareArchitect

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I engineer the compute behind the breakthrough.

FPGA × RISC-V × Cryptography

I turn demanding algorithms into timing-closed, high-performance digital systems—from architecture and RTL to verification, bring-up, and deployment.

Engineering10+Years across FPGA and embedded systems

FocusRISC-VVector acceleration and microarchitecture

Research05Publications and submitted papers

LocationNLLeiden, The Netherlands

Selected systems • 01—03

Three engineering programmes where architecture, RTL, and deployment meet.

Post-quantum computing

End-to-end implementation

High-throughput RTL

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Engineering partnership • 01

and working with me saves it

RTL • TIMING CLOSURE • HARDWARE ACCELERATION •RTL • TIMING CLOSURE • HARDWARE ACCELERATION •