Experience
The full hardware journey.
Requirements, architecture, RTL, verification, timing closure, integration, and board bring-up—owned as one connected engineering system.
Professional & academic path
PhD Candidate • Leiden University
RISC-V vector acceleration and high-performance computing for post-quantum cryptography, alongside teaching in Cryptographic Engineering and Essentials of Computer Systems.
Hardware Designer • High-Tech R&D Center
Designed low-latency DSP pipelines, multi-channel data acquisition, demodulation, polyphase filter banks, and high-speed FPGA subsystems on Zynq SoC and Kintex-7. Led custom-board bring-up and cross-functional integration.
M.Sc. Digital Electronics • Sharif University of Technology
Concurrent error detection in finite-field arithmetic using dual and normal bases. GPA: 17.87/20.
B.Sc. Electronics Engineering • Kashan University
Core training in digital systems and electronics engineering. GPA: 16.30/20.
Technical toolbox
SystemVerilog, Verilog, VHDL, HLS, microarchitecture design, RISC-V, ARM architecture, reusable IP development, CDC, and timing closure.
AMD Vivado and Vitis, ModelSim, QuestaSim, Synopsys Design Compiler, Cadence Genus/Innovus, UVM, ChipScope, MATLAB, TCL, Git, and CMake.
C/C++, Python, bare-metal programming, PCIe, SERDES, AXI4/AXI-Stream, DDR, real-time DSP, and lab validation with oscilloscopes and logic analyzers.